In wafer level packaging, circuitry is formed additively to wafers using a variety of metal deposition, lithography and metal etching processes. This circuitry can provide electrical continuity for individual circuit functions and can also provide passive device structures such as inductors and antennas.
Redistribution (RDL) is a type of circuitry that is utilized in wafer level packaging for providing flexibility on the location of bump interconnects in positions other than the original pads on the device. For example, a circuitry pattern typical of the RDL application is illustrated in FIG. 1 with the original pad location 120 and the final pad location 100 connected with a metal conductor RDL line 140. A space between the lines is indicated 160 along with an RDL line 140 and an inductor circuit 180. By relocating the pads, the die can be assembled on lower cost printed circuit boards and with more common mass production assembly equipment. Smaller geometries are desirable in redistribution and other types of circuitry to achieve miniaturization and smaller mechanical envelopes in the final assembly.
Circuitry is placed on the chips/devices while they are still in wafer form utilizing either an electroplating process or a physical vapor deposition process (PVD or sputtering). The width of the circuit lines formed during the subsequent deposition, lithography and etching processes are typically 10 to 20 microns in width and the spacing between the lines is typically 10-20 microns.
Applying circuitry by electroplating is a slow and expensive process and requires several steps including an initial PVD step of applying a seed layer of about 0.1 to 1 micron thickness that is eventually electroplated to a thicker metal thickness typically of 5 microns to 10 microns depending on the application resulting in both circuit lines and circuit spaces. FIG. 2 illustrates an exemplary process for forming an RDL circuitry structure 210 using an electroplating approach. The incoming wafer is shown at process steps 201. A structure resulting from first dielectric deposition and patterning steps are shown at 202. Next, a sputtered seed layer is deposited. The structure resulting from sputtered seed layer deposition is shown at 203. Plating resist deposition and patterning steps are illustrated at 204. An RDL copper electroplating step results in the structure illustrated at 205. The resist is then stripped and a seed layer is etched, resulting in the structure shown at 206. A second dielectric deposition and patterning step is then performed, resulting in the structure shown at 207. An under bump metal processing step is then performed, resulting in the structure shown at 208. Subsequently, metal spheres are attached, resulting in the structure illustrated at 209. Achieving circuit spaces of high resolution below 10 microns is possible because the plating is formed in photoresist channels and then the initial seed layer is etched away with minimal side wall non-uniformity. However achieving circuit lines of high resolution below 10 microns is more challenging because of the photoresist resolution.
Applying circuitry by sputtering or PVD is a lower cost, faster process because it does not need the secondary electroplating step and the lines and spaces are formed in the original seed layer which has a typical thickness of 1 to 2 microns. FIG. 3 illustrates an exemplary process for forming an RDL circuitry line 310 with a typical metal stack structure 320 using a PVD approach. With reference to the structure shown at 301, the first dielectric layer (“Polymer 1”) is coated, and the wafer is exposed, developed and cured. In a subsequent step illustrated by the structure shown at 302, the metal redistribution seed layer is sputtered with aluminum, nickel vanadium, and copper pattern and etched to form redistribution and inductor runners. At a subsequent step illustrated by the 303, a second dielectric layer (“Polymer 2”) is coated, and the wafer is exposed, developed and cured. Subsequently, metal spheres are attached, as is illustrated at 304. Circuitry formed by PVD is limited to 10-20 micron lines and spaces due to proper adhesion of the photoresist to the seed layer which is needed during the etch process for high yields.